Featured projects
current · Rust · ECS · game tooling
Pill Engine
Rust game-engine project focused on ECS, architecture, scripting experiments, hot reloading and making weird games easier to build.
Rust ECS C# Scripting Hot reload Vulkan
2021–2023 · embedded ML
BIBoP
Open hardware wearable health-monitor prototype with Blood Pressure inference from photoplethysmography sensor data.
Zephyr Embedded ML Wearables Open hardware
research · FPGA · Linux
FPGA accelerated tcpdump using eBPF
MSc thesis project on hardware acceleration of packet capture in embedded Linux using FPGA programmable logic.
FPGA Linux eBPF Networking Buildroot
Thesis note · PDF · Talk
Archive / smaller things
2025–now
Game jams / Sticky Piston Studios
Being a hardcore gamejammer, I am familiar with Unity, custom game engines and other popular tools of the trade.
2021
C++ to Rust - or how to render your mindset
I will reimplement the amazing tutorial on Ray Tracing in One Weekend in the Rust programming language.
2020–2021
Rustalizer
older
PolyEngine
older
Envidrawer
Thesis abstracts
FPGA accelerated tcpdump using eBPF
With the rise of the Internet of Things and the proliferation of embedded devices equipped with an accelerator arose a need for efficient resource utilization. Hardware acceleration is a complex topic that requires specialized domain knowledge about the platform and different trade-offs that have to be made, especially in the area of power consumption.
The thesis focuses on accelerating networking packets utilizing a Field Programmable Gate Array in an embedded Linux System. The solution is based on a custom Linux distribution assembled using the Buildroot tool, specially configured and patched Linux kernel, uboot bootloader, and the programmable logic for packet acceleration.
Keywords: Field Programmable Gate Array, Acceleration, Networking, Embedded Linux
PDF: FPGA accelerated tcpdump using eBPF
FPGA based hardware accelerator for musical synthesis for Linux system
Work focuses on realizing an audio synthesizer in a System on Chip, utilizing FPGA hardware resources. It covers aspects of sound synthesis in hardware and writing Linux Device Drivers for communicating with the FPGA utilizing DMA.
An optimal approach to synthesis is researched and assessed and LUT-based interpolation is asserted as the best choice for this project. A novel State Variable IIR Filter is implemented in Verilog and utilized.
Keywords: FPGA, Sound Synthesis, SoC, DMA, SVF
PDF: FPGA based hardware accelerator for musical synthesis for Linux system